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XC17V00 Series Configuration PROMs
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DS073 (v1.12) November 13, 2008
Product Specification
Features
* One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx(R) FPGA devices Simple interface to the FPGA Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Low-power CMOS floating-gate process 3.3V supply voltage Guaranteed 20 year life data retention * * * * Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20(1) Programming support by leading programmer manufacturers Design support using the ISE(R) FoundationTM and ISE WebPACKTM software Dual configuration modes for the XC17V16 and XC17V08(1) devices

* * * * * *
Serial slow/fast configuration (up to 20 Mb/s) Parallel (up to 160 Mb/s at 20 MHz)
Description
Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, costeffective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1 and Figure 2 for simplified block diagrams of the XC17V00 family. The XC17V00 PROM can configure a Xilinx FPGA using the FPGA serial configuration mode interface. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. The XC17V08(1) and XC17V16 PROM can optionally configure a Xilinx FPGA using the FPGA Parallel (SelectMAP) configuration mode interface. When the FPGA is in Master SelectMAP mode, the FPGA generates the configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP mode, an external, free-running oscillator generates the configuration clock that drives the PROM and the FPGA. After the rising configuration clock (CCLK) edge, data is available on the PROMs DATA (D0-D7) pins. The data is clocked into the FPGA on the following rising edge of the CCLK (Figure 3). Multiple PROMs can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx ISE Foundation or ISE WebPACK software compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Discontinued part number and package combinations remain in this data sheet for reference.
(c) Copyright 2000-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
X-Ref Target - Figure 1
VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
EPROM Cell Matrix
Output
OE DATA
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, (does not show programming circuit)
X-Ref Target - Figure 2
XC17V02(1),
and XC17V01
VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
BUSY EPROM Cell Matrix Output 8 OE D0 Data (Serial or Parallel Mode)
7 7
D[1:7] (SelectMAP Interface)
DS073_02_031506
Figure 2: Simplified Block Diagram for XC17V16 and (does not show programming circuit)
XC17V08(1)
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Pin Description
DATA[0:7]
The array data value corresponding to the internal address counter location is output on enabled DATA[0-7] output pin(s) when CE is active, OE is active, and the internal address counter has not incremented beyond its Terminal Count (TC) value. Otherwise, all data pins are in a high impedance state when CE is inactive, OE is inactive, or the internal address counter has incremented beyond its Terminal Count (TC) value. The XC17V01, XC17V02, and XC17V04 have only the single DATA output pin for connection to the FPGA serial configuration data input pin. The XC17V08 and XC17V16 have the D[0-7] output pins. During device programming, the XC17V08 and XC17V16 must be programmed for use in either serial output mode or parallel output mode. For XC17V08 and XC17V16 devices programmed to serial output mode, only the D0 pin is enabled for data output to the Virtex(R) series FPGA serial configuration data input pin. In serial mode, the D[1-7] output pins remain in high impedance state and may be unconnected. For XC17V08 and XC17V16 devices programmed to parallel output mode, all D[0-7] output pins are enabled for byte-wide data output to the FPGA SelectMAP configuration data input pins. The DATA/D0 pin is a bidirectional I/O during device programming.
CEO
Chip Enable Output is connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE goes inactive or CE goes High.
BUSY (XC17V16 and XC17V08 Only)
Asserting the BUSY input High prevents rising edges on CLK from incrementing the internal address counter and maintains current data on the data pins. Note: If the BUSY pin is floating, then the programmable option
to internally tie BUSY to an internal pull-down resistor must be set during device programming.
VPP
Programming voltage. No overshoot above the specified maximum voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Caution! Do not leave VPP floating!
VCC and GND
Positive supply and ground pins.
CLK
Each rising edge on the CLK input increments the internal address counter, when CE is active, OE is active, the internal address counter has not incremented past its Terminal Count (TC) value, and BUSY is Low. Note: The BUSY condition applies to only the XC17V08 and
XC17V16.
PROM Pinouts for XC17V16 and XC17V08
Pins not listed in Table 1 are "no connect." Table 1: Pinouts for XC17V16 and XC17V08(1)
Pin Name
BUSY D0 D1
44-pin VQFP (VQ44)
24 40 29 42 27 9 25 14 19 43 13 15 6, 18, 28, 37, 41 21
44-pin PLCC (PC44)
30 2 35 4 33 15 31 20 25 5 19 21 3, 12, 24, 34, 43 27
RESET/OE
The polarity of this input pin is programmable as either RESET/OE or OE/RESET. The polarity is set at the time of device programming. The device default is active-High RESET, but compatibility with Xilinx FPGAs requires the polarity to be programmed with an active-Low RESET. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state.
D2 D3 D4 D5 D6 D7 CLK RESET/OE (OE/RESET) CE GND CEO
CE
When High, this pin holds the internal address counter in reset, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode.
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Pin Name
VPP VCC Notes:
1.
44-pin VQFP (VQ44)
35 8, 16, 17, 26, 36, 38
44-pin PLCC (PC44)
41 14, 22, 23, 32, 42, 44
NC CLK D2 GND DATA(D0) NC VCC GND NC NC NC NC NC GND NC VCC D4 NC NC 7 8 9 10 11 12 13 14 15 16 17
Table 1: Pinouts for XC17V16 and XC17V08(1)(Cont'd)
6 5 4 3 2 1 44 43 42 41 40
VPP NC
VCC
Specific part number and package combinations have been discontinued. Refer to XCN07010.
Capacity
Table 2: Device Capacities
Devices
XC17V16 XC17V08(1) Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
PC44 Top View
Configuration Bits
16,777,216 8,388,608
39 38 37 36 35 34 33 32 31 30 29
NC NC NC NC D1 GND D3 VCC D5 BUSY NC
Pinout Diagrams for XC17V16 and XC17V08
NC CLK D2 GND DATA(D0) NC VCC GND VCC VPP NC
NC OE/RESET D6 CE VCC VCC GND D7 NC CEO NC
18 19 20 21 22 23 24 25 26 27 28
DS073_13_101502
PROM Pinouts for XC17V04, XC17V02, and XC17V01
Pins not listed in Table 3 are "no connect."
33 32 31 30 29 28 27 26 25 24 23 NC NC NC NC D1 GND D3 VCC D5 BUSY NC
NC NC NC NC NC GND
NC
VCC D4 NC NC
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34
Table 3: Pinouts for XC17V04, XC17V02, and XC17V01
Pin Name
DATA CLK RESET/OE (OE/RESET) CE GND
VQ44 Top View
8-pin VOIC (V08)
(1)
20-pin SOIC (SO20)
(1,3)
20-pin PLCC (PC20)
(1,2)
44-pin VQFP (VQ44)
(2)
44-pin PLCC (PC44)
(2)
1 2 3 4 5 6 7 8
1 3 8 10 11 13 18 20
1 3 8 10 11 13 18 20
40 43 13 15 18, 41 21 35 38
2 5 19 21 24, 3 27 41 44
NC OE/RESET D6 CE VCC VCC GND D7 NC CEO NC
12 13 14 15 16 17 18 19 20 21 22
CEO VPP
DS073_12_101502
VCC Notes:
1. 2. 3.
XC17V01 available in these packages. XC17V02 and XC17V04 available in these packages. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Devices
XC17V04 XC17V02(1) XC17V01 Notes:
1.
Configuration Bits
4,194,304 2,097,152 1,679,360
Specific part number and package combinations have been discontinued. Refer to XCN07010.
Pinout Diagrams for XC17V04, XC17V02(1), and XC17V01
NC CLK NC GND DATA(D0) NC VCC NC
NC NC NC NC NC NC NC NC NC NC NC
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
VPP NC
Table 4: Device Capacities
NC CLK NC GND DATA(D0) NC VCC NC
Capacity
NC
PC44 Top View
(See Note 2)
39 38 37 36 35 34 33 32 31 30 29
NC NC NC NC NC NC NC NC NC NC NC
VPP NC
NC
NC NC NC NC NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
VQ44 Top View
(See Note 2)
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC NC
NC OE/RESET NC CE NC NC GND NC NC CEO NC
44 43 42 41 40 39 38 37 36 35 34
18 19 20 21 22 23 24 25 26 27 28
DS073_08_100702
DATA(D0) CLK OE/RESET CE
1 2
8
VCC VPP CEO GND
12 13 14 15 16 17 18 19 20 21 22
3 (See Note 1) 6 4 5
VO8 7 Top View
NC OE/RESET NC CE NC NC GND NC NC CEO NC
DS073_09_110102
DS073_07_100702
DATA(D0) NC CLK NC NC NC NC OE/RESET NC CE
1 20 2 19 3 18 SO20 17 4 Top 16 5 View 15 6 (See 7 14 8 Notes 1, 3) 13 9 12 10 11
VCC NC VPP NC NC NC NC CEO NC GND
DS073_10_082108
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs Table 5: Xilinx FPGAs and Compatible PROMs (Cont'd)
CLK NC DATA(D0) VCC NC
Device
XCV600 XCV800
Configuration Bits
3,607,968 4,715,616 6,127,744 630,048 863,840 1,442,016 1,875,648 2,693,440 3,430,400 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712 439,264 1,047,616 1,699,136 3,223,488 5,214,784 7,673,024 11,316,864 13,271,936
PROM
XC17V04 XC17V08(1) XC17V16 XC17V08(1) XC17V16 XC17V01 XC17V01 XC17V01 XC17V02(1) XC17V04 XC17V04 XC17V04 XC17V04 XC17V08(1) XC17V16 XC17V08(1) XC17V16 XC17V08(1) XC17V16 XC17V16 XC17V16 XC17V16 XC17V01 XC17V01 XC17V02(1) XC17V04 XC17V04 XC17V08(1) XC17V16 XC17V08(1) XC17V16 XC17V16 XC17V16
9 10 11 12 13
NC NC NC NC OE/RESET
18 4 17 5 PC20 6 Top View 16 7 (See Notes 1, 2, 3)15 14 8
3 2 1 20 19
VPP NC NC NC NC
XCV1000 XCV50E XCV100E XCV200E
NC CE GND NC CEO
XCV300E
DS073_11_062508
XCV400E XCV405E XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Notes:
1.
Notes:
1. 2. 3. XC1701 is available in these packages. XC1702 and XC1704 are available in these packages. Specific part number and package combinations have been discontinued. Refer to XCN07010.
Xilinx FPGAs and Compatible PROMs
Table 5: Xilinx FPGAs and Compatible PROMs
Device
XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400
Configuration Bits
360,096 635,296 1,697,184 2,761,888 4,082,592 5,659,296 7,492,000 10,494,368 15,659,936 21,849, 504 29,063,072 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048
PROM
XC17V01 XC17V01 XC17V02(1) XC17V04 XC17V04 XC17V04 XC17V08(1) XC17V16 XC17V08(1) XC17V16 XC17V16 XC17V16 XC17V16+XC17V08(1) 2 of XC17V16 2 of XC17V16 XC17V01 XC17V01 XC17V01 XC17V01 XC17V02(1) XC17V04 XC17V04
Specific part number and package combinations have been discontinued. Refer to XCN07010. For some devices, the original PROM recommendation is shown along with the replacement PROM.
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Controlling PROMs
Connecting the FPGA device with the PROM. * * * * The DATA output(s) of the PROM(s) drives the configuration data input(s) of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. The PROM CE input is best connected to the FPGA DONE pin(s) and a pullup resistor. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 15 mA maximum. SelectMAP mode is similar to Slave Serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 3. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA PROGRAM pin goes Low, assuming the PROM reset polarity option has been inverted.
*
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.
*
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only one serial data line, two control lines, and one clock line are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up/down resistor or keeper circuit.
DS073 (v1.12) November 13, 2008 Product Specification
Selecting Reset Polarity and Configuration Modes
The OE/RESET input polarity is programmable on all XC17V00 PROMs. In addition, the XC17V08 and XC17V16 can accommodate either serial or parallel configuration mode. The reset polarity and configuration mode are selectable through the programmer software. For compatibility with Xilinx FPGAs, the OE/RESET polarity must be programmed with RESET active-Low.
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XC17V00 Series Configuration PROMs
Table 6: Truth Table for XC17V00 Control Inputs
Control Inputs RESET(1)
Inactive Active Inactive Active Notes:
1. 2. The XC17V00 RESET input has programmable polarity TC = terminal count, highest address value.
CE
Low Low High High
Internal Address
If address < TC(2): increment If address > TC(2): don't change Held reset Not changing Held reset
Outputs DATA
Active High-Z High-Z High-Z High-Z
CEO
High Low High High High
ICC
Active Reduced Active Standby Standby
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
X-Ref Target - Figure 3
DOUT VCC
FPGA
Modes(1)
4.7K VCC 4.7K VCC
(2)
OPTIONAL Daisy-chained FPGAs with different configurations OPTIONAL Slave FPGAs with identical configurations VCC VCC
DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer)
VCC DATA CLK CE
Vpp BUSY CEO
VCC BUSY DATA CLK CE
Vpp
First PROM
OE/RESET
Cascaded PROM
OE/RESET
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide. (2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Master Serial Mode
I/O(1) I/O(1) Modes(3) CS WRITE 1K 1K 3.3V VCC
(2)
External Osc(4)
VCC
VCC
FPGA
BUSY CCLK PROGRAM D[0:7] DONE INIT
VCC
Vpp BUSY
VCC
Vpp
4.7K First CLK PROM 8 D[0:7] CE OE/RESET
CEO
BUSY Second CLK PROM CEO D[0:7] CE OE/RESET
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown. (2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide. (3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide. (4) External oscillator required for FPGA slave SelectMAP modes.
SelectMAP Mode, XC17V16 and XC17V08(1) only.
DS073_03_102708
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode (dotted lines indicate optional connection)
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Absolute Maximum Ratings(1)
Symbol
VCC VPP VIN VTS TSTG TJ Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Description
Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Junction temperature
Conditions
-0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +125
Units
V V V V C C
Operating Conditions (3V Supply)
Symbol
VCC(1) TVCC(2) Notes:
1. 2. During normal read operation VPP must be connected to VCC. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly.
Description
Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) VCC rise time from 0V to nominal voltage Commercial Industrial
Min
3.0 3.0 1.0
Max
3.6 3.6 50
Units
V V ms
DC Characteristics Over Operating Condition
Symbol
VIH VIL VOH VOL ICCA ICCA ICCS IL CIN COUT Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
Description
High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, active mode (at maximum frequency) (XC17V16 and XC17V08(1) only) Supply current, active mode (at maximum frequency) (XC17V04, XC17V02(1), and XC17V01(1) only) Supply current, standby mode Input or output leakage current Input capacitance (VIN = GND, f = 1.0 MHz) Output capacitance (VIN = GND, f = 1.0 MHz)
Min
2 0 2.4 - - - - -10 - -
Max
VCC 0.8 - 0.4 100 15 1 10 15 15
Units
V V V V
mA mA
mA A pF pF
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V04, XC17V02, and XC17V01
X-Ref Target - Figure 4
TCEH
CE
TSCE TSCE THCE
RESET/OE
TLC THC THOE TCYC
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity. Timing specifications are identical for both polarity settings. 2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate FPGA data sheet or user guide for actual configuration signal sequences.
DS073_04_14102005
Symbol
TOE TCE TCAC TDF TOH TCYC TLC THC TSCE THCE THOE TCEH Notes:
1. 2. 3. 4. 5. 6.
Description
OE to data delay CE to data delay CLK to data delay CE or OE to data float delay(2,3) CLK(3)
Min
- - - - 0 67 25 25 25 0 25 20
Max
30 45 45 50 - - - - - - - -
Units
ns ns ns ns ns ns ns ns ns ns ns ns
Data hold from CE, OE, or Clock periods CLK Low CLK High time(3) time(3)
CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) CE High time (guarantees counters are reset)
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. If TCEH High, 2 s, TCE = 2 s. If THOE High, 2 s, TOE = 2 s.
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
TCEH
CE
TSCE TSCE THCE
RESET/OE(1)
TLC THC THOE TCYC
CLK
TOE TCE TCAC TOH TDF
DATA
TSBUSY THBUSY TOH
BUSY(2)
Note: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity. Timing specifications are identical for both polarity settings. 2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time TCAC after the rising CLK edge. If BUSY is active (High) during a rising CLK edge, then there is no corresponding change to DATA.
DS073_05_031606
Symbol
TOE TCE TCAC TDF TOH TCYC TLC THC TSCE THCE THOE TSBUSY THBUSY TCEH Notes:
1. 2. 3. 4. 5. 6. 7.
Description
OE to data delay CE to data delay CLK to data delay(2) CE or OE to data float delay(3,4) Data hold from CE, OE, or CLK(4) Clock periods CLK Low time(4) CLK High time(4) CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) BUSY setup time BUSY hold time CE High time (guarantees counters are reset)
Min
- - - - 0 50 25 25 25 0 25 5 5 20
Max
15 20 20 35 - - - - - - - - - -
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC test load = 50 pF. When BUSY = 0. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. If TCEH High, 2 s, TCE = 2 s. If THOE High, 2 s, TOE = 2 s.
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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition When Cascading
X-Ref Target - Figure 6
RESET/OE
CE
CLK
TCDF TOCE First Bit TOOE
DATA
Last Bit TOCK
CEO
Notes: 1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity. Timing specifications are identical for both polarity settings. 2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation. The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control from one PROM to the next.
DS026_07_102005
Symbol
TCDF TOCK TOCE TOOE Notes:
1. 2. 3. 4.
Description
CLK to data float CLK to CEO CE to CEO delay(2,3) delay(3) delay(3)
Min
- - - -
Max
50 30 35 30
Units
ns ns ns ns
delay(3)
RESET/OE to CEO
AC test load = 50 pF. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. Guaranteed by design, not tested. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
Ordering Information
XC17V16 PC44 C
Device Number XC17V16 XC17V04 XC17V01 Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Chip Carrier VO8 = 8-pin Plastic Small Outline Thin Package PC20 = 20-pin Plastic Leaded Chip Carrier Operating Range/Processing C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
DS073 (v1.12) November 13, 2008 Product Specification
www.xilinx.com 13
R
XC17V00 Series Configuration PROMs
Valid Ordering Combinations
XC17V16VQ44C XC17V16PC44C XC17V16VQ44I XC17V16PC44I XC17V04PC20C XC17V04PC44C XC17V04VQ44C XC17V04PC20I XC17V04PC44I XC17V04VQ44I XC17V01VO8C
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16 PC44 C
Device Number XC17V16 XC17V08(1) XC17V04 XC17V02(1) XC17V01
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
Operating Range/Processing Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Chip Carrier VO8 = 8-pin Plastic Small Outline Thin Package PC20 = 20-pin Plastic Leaded Chip Carrier SO20 = 20-pin Plastic Small Outline Package(1) C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
DS073 (v1.12) November 13, 2008 Product Specification
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XC17V00 Series Configuration PROMs
Revision History
The following table shows the revision history for this document.
.
Date
07/26/00 10/09/00 11/16/00 02/20/01 04/04/01 10/09/01 02/27/02 06/14/02 07/29/02 11/05/02
Version
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Initial Xilinx release. Updated 20-pin PLCC Pinouts.
Revision
Updated pinouts for XC17V16 and XC17V08, ICCA DC Characteristic from standby to active mode; CIN and COUT from 10 pF to 15 pF, added ICCS for XC17V16 and XC17V08 at 500 A. Added note to pinouts for "no connect," updated Figure 3. Added XC2V products to Compatible PROM table, updated Figure 3, updated text for Virtex-II FPGAs. Corrected bitstream length for SCV405E, added power-on supply requirements and note for power-on reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3, and updated FPGA list. Added Virtex-II ProTM FPGAs to the , page 6. Made additions and changes to Xilinx FPGAs and Compatible PROMs, page 6. Added Virtex-II Pro FPGAs to , page 6. Added pinout diagrams, changed , page 6, and added footnotes to AC Characteristics over Operating Condition for XC17V04, XC17V02, and XC17V01, page 11 and AC Characteristics over Operating Condition for XC17V16 and XC17V08, page 12. Added Spartan-3 FPGAs to Truth Table for XC17V00 Control Inputs, page 8. * * * * Figure 2, page 2 updated to show correct three-state control on output data buses. Corrected XC3S50 bitstream size in Xilinx FPGAs and Compatible PROMs, page 6. Added section Selecting Reset Polarity and Configuration Modes, page 7. Removed maximum soldering temperature (TSOL) from "Absolute Maximum Ratings(1)," page 10. Refer to Xilinx Device Package User Guide for package soldering guidelines. * Added notes to timing diagram under AC Characteristics over Operating Condition for XC17V04, XC17V02, and XC17V01, page 11 for clarification. * Added notes and updated timing diagram AC Characteristics over Operating Condition for XC17V16 and XC17V08, page 12 for clarification. * Reversed polarity of RESET/OE signal in timing diagram under , page 13 for consistency and added notes for clarification.
04/10/03 06/07/07
1.10 1.11
11/13/08
1.12
* Added support for discontinued device and package combinations per XCN07010. * Added TJ to "Absolute Maximum Ratings(1)," page 10. * Updated Figure 3.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
DS073 (v1.12) November 13, 2008 Product Specification
www.xilinx.com 15

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